8T(kfragment@0__overlay__ disabledfragment@1__overlay__ disabledfragment@2__overlay__)pcie-ep@2900000:ti,j784s4-pcie-ep@Ep Iintd_cfguser_cfgregmem Slink_state c>n L Lfck pcie-phypcie-ep@2910000:ti,j784s4-pcie-ep@Ep Iintd_cfguser_cfgregmem Slink_state cJn M Mfck pcie-phy__fixups__/fragment@0:target:0/fragment@1:target:0/fragment@2:target:0+/fragment@2/__overlay__:interrupt-parent:0> /fragment@2/__overlay__/pcie-ep@2900000:ti,syscon-pcie-ctrl:0p+/fragment@2/__overlay__/pcie-ep@2900000:power-domains:0/fragment@2/__overlay__/pcie-ep@2910000:power-domains:0b2/fragment@2/__overlay__/pcie-ep@2900000:clocks:0/fragment@2/__overlay__/pcie-ep@2910000:clocks:0/:/fragment@2/__overlay__/pcie-ep@2900000:phys:0>M/fragment@2/__overlay__/pcie-ep@2910000:ti,syscon-pcie-ctrl:0/X/fragment@2/__overlay__/pcie-ep@2910000:phys:0 targetstatus#address-cells#size-cellsinterrupt-parentcompatibleregreg-namesinterrupt-namesinterruptsti,syscon-pcie-ctrlmax-link-speednum-lanespower-domainsclocksclock-namesmax-functionsmax-virtual-functionsdma-coherentphysphy-namespcie0_rcpcie1_rccbass_maingic500pcie0_ctrlk3_pdsk3_clksserdes1_pcie0_linkpcie1_ctrlserdes0_pcie1_link