8H(Afragment@0__overlay__ disabledfragment@1__overlay__)pcie-ep@2900000:ti,j721e-pcie-ep@Ep Iintd_cfguser_cfgregmem Slink_state c>n@p  fck pcie-phy__fixups__/fragment@0:target:0/fragment@1:target:0+/fragment@1/__overlay__:interrupt-parent:0>/fragment@1/__overlay__/pcie-ep@2900000:ti,syscon-pcie-ctrl:08 /fragment@1/__overlay__/pcie-ep@2900000:power-domains:01'/fragment@1/__overlay__/pcie-ep@2900000:clocks:0///fragment@1/__overlay__/pcie-ep@2900000:phys:0 targetstatus#address-cells#size-cellsinterrupt-parentcompatibleregreg-namesinterrupt-namesinterruptsti,syscon-pcie-ctrlmax-link-speednum-lanespower-domainsclocksclock-namesmax-functionsmax-virtual-functionsdma-coherentphysphy-namespcie0_rccbass_maingic500scm_confk3_pdsk3_clksserdes0_pcie_link