P8 ( fragment@0/__overlay__hdmi-connector hdmi-connectorhdmia". 6 portendpoint@Pdvi-bridgeXg ti,tfp410 sport@0endpoint@Pport@1endpoint@Pfragment@1__overlay__main-i2c1-exp6-default-pinsdPdss-vout0-default-pinsX \ ` d h l p t x |       0 4 8 < @ D $ (     Pfragment@2__overlay__p14-hog: VINOUT_MUX_SEL0p15-hog: VINOUT_MUX_SEL1fragment@3__overlay__Xggpio@21 ti,tca6416!default-8MPp11-hog:  HDMI_DDC_OEfragment@4__overlay__defaultfragment@5__overlay__Xgport@1endpoint@P__fixups__J^/fragment@0/__overlay__/hdmi-connector:ddc-i2c-bus:0/fragment@3:target:0h/fragment@1:target:0r/fragment@2:target:03w/fragment@3/__overlay__/gpio@21:interrupt-parent:0/fragment@4:target:0/fragment@5:target:0__local_fixups__fragment@0__overlay__hdmi-connector6portendpoint@dvi-bridgesport@0endpoint@port@1endpoint@fragment@3__overlay__gpio@21fragment@4__overlay__fragment@5__overlay__port@1endpoint@ target-pathcompatiblelabeltypeddc-i2c-busdigitalhpd-gpiosremote-endpointphandle#address-cells#size-cellspowerdown-gpiosregpclk-sampletargetpinctrl-single,pinsgpio-hogoutput-lowline-nameoutput-highclock-frequencygpio-controller#gpio-cellspinctrl-namespinctrl-0interrupt-parentinterruptsinterrupt-controller#interrupt-cellsmain_i2c1main_pmx0exp1main_gpio1dssdss_ports