Y8T(T4STMicroelectronics STM32MP257F-EV1 Evaluation Board!!st,stm32mp257f-ev1st,stm32mp257cpuscpu@0!arm,cortex-a35,cpu8?@fdma-controller@40420000!st,stm32mp25-dma38@BsABCDEFGHIJKLMNOPgbus@42080000!st,stm32mp25-rifscsimple-bus8Bk spi@400b0000!st,stm32mp25-spi8@  sq    disabledspi@400c0000!st,stm32mp25-spi8@  s}    disableddefaultsleep  serial@400e0000!st,stm32h7-uart8@ ss  okaydefaultidlesleep serial@400f0000!st,stm32h7-uart8@ st  ! disabledserial@40100000!st,stm32h7-uart8@ s~  " disabledserial@40110000!st,stm32h7-uart8@ s  # disabledi2c@40120000!st,stm32mp25-i2c8@event sl  * ) disabledi2c@40130000!st,stm32mp25-i2c8@event sn  + *okaydefaultsleep d$ i2c@40140000!st,stm32mp25-i2c8@event s   , + disabledi2c@40150000!st,stm32mp25-i2c8@event s   - , disabledi2c@40160000!st,stm32mp25-i2c8@event s   . - disabledi2c@40170000!st,stm32mp25-i2c8@event s  / . disabledi2c@40180000!st,stm32mp25-i2c8@event s  0 / disabledserial@40220000!st,stm32h7-uart8@" s  $ disableddefaultidlesleep<spi@40230000!st,stm32mp25-spi8@# sp    disabledspi@40240000!st,stm32mp25-spi8@$ s    disabledspi@40280000!st,stm32mp25-spi8@( s    disabledserial@402c0000!st,stm32h7-uart8@, s  ' disabledserial@40330000!st,stm32h7-uart8@3 sr   disabledspi@40350000!st,stm32mp25-spi8@5 s    disabledspi@40360000!st,stm32mp25-spi8@6 s    disabledserial@40370000!st,stm32h7-uart8@7 s  % disabledserial@40380000!st,stm32h7-uart8@8 s  & disabledspi@46020000!st,stm32mp25-spi8F s *   disableddefaultsleepi2c@46040000!st,stm32mp25-i2c8Fevent s + 1 0 disableddefaultsleep 9$mmc@48220000,!st,stm32mp25-sdmmc2arm,pl18xarm,primecellL518H"D# s{ 9 capb_pclk Eo' Lokaydefaultopendrainsleep  ethernet@482c0000#!st,stm32mp25-dwmacsnps,dwmac-5.208H,@ stmmacethmacirq6cstmmacethmac-clk-txmac-clk-rxptp_refethstpeth-ck0 I H G > M <" 5!HQZ"0 < disabledrx-queues-configdk queue0queue1tx-queues-configzk!queue0queue1queue2queue3stmmac-axi-configkethernet@482d0000#!st,stm32mp25-dwmacsnps,dwmac-5.208H-@ stmmacethmacirq6cstmmacethmac-clk-txmac-clk-rxptp_refethstpeth-ck0 L K J ? N =#"$5%HQZ"4 =okaydefaultsleep&'( rgmii-idrx-queues-configdk$queue0queue1tx-queues-configzk%queue0queue1queue2queue3stmmac-axi-configk#mdio!snps,dwmac-mdioethernet-phy@1!ethernet-phy-id001c.c9168', )k(vdec@480d0000!st,stm32mp25-vdec8H  su  Yvenc@480e0000!st,stm32mp25-venc8H s  Zefuse@44000000!st,stm32mp25-bsec8Dpart_number_otp@248$package_otp@1e88clock-controller@44200000!st,stm32mp25-rcc8D |ACEBDF@      !"#$%&'()*+,-./0123456789:;<=>?MNOPQRSJ* k interrupt-controller@44220000!st,stm32mp1-extisysconRA8D"`  lnrst~pq} mok+syscon@44230000!st,stm32mp25-syscfgsyscon8D#k"pinctrl@44240000!st,stm32mp257-pinctrl D$ +  +`'k,gpio@442400002BRA8YNGPIOAokay[b,gpio@442500002BRA8ZNGPIOBokay[b,gpio@442600002BRA8[NGPIOCokay[b, gpio@442700002BRA8\NGPIODokay[b,0kgpio@442800002BRA8]NGPIOEokay[b,@gpio@442900002BRA8^NGPIOFokay[b,Pgpio@442a00002BRA8_NGPIOGokay[b,`k)gpio@442b00002BRA8`NGPIOHokay[ b,r gpio@442c00002BRA8aNGPIOIokay[b,gpio@442d00002BRA8 bNGPIOJokay[b,gpio@442e00002BRA8 cNGPIOKokay[b,eth2-rgmii-0k&pins1n' ( ) * $ upins2 nX W & upins3n% upins4n` , Y + # upins5nV ueth2-rgmii-sleep-0k'pins<n'()*$XW&%`,Y+#Vi2c2-0kpinsn  ui2c2-sleep-0kpinsnsdmmc1-b4-0kpins1nD E @ A B upins2nC usdmmc1-b4-od-0kpins1nD E @ A upins2nC upins3nB usdmmc1-b4-sleep-0kpinsnDE@ACBspi3-0k pins1nupins2nuspi3-sleep-0k pins1 nusart2-0k pins1nupins2n uusart2-idle-0kpins1npins2n uusart2-sleep-0kpinsnusart6-0kpins1n]eupins2n^_usart6-idle-0kpins1n]_pins2neupins3n^usart6-sleep-0kpinsn]e_^pinctrl@46200000!st,stm32mp257-z-pinctrl F +  +`k-gpio@462000002BRA8dNGPIOZ okay[ b- i2c8-0kpinsn  ui2c8-sleep-0kpinsnspi8-0kpins1nupins2nuspi8-sleep-0kpins1 ninterrupt-controller@46230000!st,stm32mp1-extisysconRA8F#8    aliases&/soc@0/bus@42080000/ethernet@482d0000$/soc@0/bus@42080000/serial@400e0000$/soc@0/bus@42080000/serial@40220000chosenserial0:115200n8memory@80000000,memory8reserved-memoryfw@80000000!shared-dma-pool8 #address-cells#size-cellsmodelcompatibledevice_typeregenable-methodpower-domainspower-domain-namesphandleinterruptsinterrupt-affinityinterrupt-parentarm,smc-idstatustimeout-sec#clock-cellsclock-frequencylinaro,optee-channel-id#reset-cellsregulator-nameregulator-min-microvoltregulator-max-microvolt#interrupt-cellsinterrupt-controller#power-domain-cellsalways-onrangesclocks#dma-cells#access-controller-cellsresetsaccess-controllerspinctrl-namespinctrl-0pinctrl-1pinctrl-2interrupt-namesi2c-scl-rising-time-nsi2c-scl-falling-time-nsuart-has-rtsctsarm,primecell-periphidclock-namescap-sd-highspeedcap-mmc-highspeedmax-frequencycd-gpiosdisable-wpst,neg-edgebus-widthvmmc-supplyvqmmc-supplyreg-namesinterrupts-extendedsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,pblsnps,tsost,sysconsnps,rx-queues-to-usesnps,tx-queues-to-usesnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtmax-speedphy-handlephy-modereset-assert-usreset-deassert-usreset-gpiosbitsst,syscfgpins-are-numberedst,packagegpio-controller#gpio-cellsst,bank-namengpiosgpio-rangespinmuxbias-disabledrive-push-pullslew-ratedrive-open-drainbias-pull-upst,bank-ioportethernet0serial0serial1stdout-pathno-map