Ð þíóh¤(O<ðð°Kà ,xnano,x5realtek,rtd1295 7Xnano X5reserved-memory =rpc@1f000Dðrpc@1ffe000Dÿà@tee@10100000DðHarm-pmu,arm,cortex-a53-pmu O0Zosc ,fixed-clockm›üÀ}Šosc27Msoc@0 ,simple-bus =ð€€€bus@98000000 ,simple-busD˜   =˜ syscon@0,sysconsimple-mfdD¥  =reset-controller@0,snps,dw-low-resetD²reset-controller@4,snps,dw-low-resetD²reset-controller@8,snps,dw-low-resetD²reset-controller@50,snps,dw-low-resetDP²syscon@7000,sysconsimple-mfdDp¥  =preset-controller@88,snps,dw-low-resetDˆ²watchdog@680,realtek,rtd1295-watchdogD€¿serial@800,snps,dw-apb-uartDÆ¥m›üÀÐ×okaysyscon@1a000,sysconsimple-mfdD ¥  = syscon@1b000,sysconsimple-mfdD°¥  =°serial@200,snps,dw-apb-uartDÆ¥m¿ÌÐ ×disabledserial@400,snps,dw-apb-uartDÆ¥m¿ÌÐ ×disabledsyscon@1d000,sysconsimple-mfdDÐ ¥  =Ð interrupt-controller@ff011000 ,arm,gic-400 Dÿÿ ÿ@ ÿ`  O Þócpus cpu@0cpu,arm,cortex-a53D cpu@1cpu,arm,cortex-a53D cpu@2cpu,arm,cortex-a53D cpu@3cpu,arm,cortex-a53D l2-cache,cache!- timer,arm,armv8-timer0O   memory@1f000memoryDð?þaliases+;/soc@0/bus@98000000/syscon@7000/serial@800chosenCserial0:115200n8 interrupt-parent#address-cells#size-cellscompatiblemodelrangesregno-mapinterruptsinterrupt-affinityclock-frequency#clock-cellsclock-output-namesphandlereg-io-width#reset-cellsclocksreg-shiftresetsstatusinterrupt-controller#interrupt-cellsdevice_typenext-level-cachecache-levelcache-unifiedserial0stdout-path