Pq8L(Ld)microchip,sparx5-pcb135microchip,sparx5 +-7Sparx5 PCB135 Reference Board (eMMC enabled)aliases=/axi@600000000/spi@600104000 B/axi@600000000/serial@600100000 J/axi@600000000/serial@600102000chosenRserial0:115200n8cpus+cpu-mapcluster0core0^core1^cpu@0arm,cortex-a53bcpun rspin-tablecpu@1arm,cortex-a53bcpun rspin-tablel2-cache0cachearm-pmuarm,cortex-a53-pmu psci arm,psci-0.2ysmc disabledtimerarm,armv8-timer0   lcpll-clk fixed-clockclock-controller@61110000cmicrochip,sparx5-dpll n $ ahb-clk fixed-clock沀sys-clk fixed-clock%@@axi@600000000 simple-bus+interrupt-controller@600300000 arm,gic-v3+<n04  ! "   syscon@600000000.microchip,sparx5-cpu-sysconsysconsimple-mfd nmux-controller mmio-mux)< reset-controller@611010008microchip,sparx5-switch-reset nJgcbTaserial@600100000lvdefault ns16550a n  okayserial@600102000l vdefault ns16550a n  okayspi@600104000+microchip,sparx5-spi n@@ okayspi@0spi-mux +nflash@9jedec,spi-norzn timer@600105000snps,dw-apb-timer nPtimer mmc@600800000microchip,dw-sparx5-sdhciokay nl vdefault core / u pinctrl@6110101e0microchip,sparx5-pinctrlnP 0< @  cs1-pinsHGPIO_16Msics2-pinsHGPIO_17Msics3-pinsHGPIO_18Msisi2-pinsHGPIO_39GPIO_40GPIO_41Msi2sgpio-pinsHGPIO_0GPIO_1GPIO_2GPIO_3Msg0sgpio1-pinsHGPIO_4GPIO_5GPIO_12GPIO_13Msg1sgpio2-pins HGPIO_30GPIO_31GPIO_32GPIO_33Msg2uart-pinsHGPIO_10GPIO_11Muartuart2-pinsHGPIO_26GPIO_27Muart2 i2c-pinsHGPIO_14GPIO_15Mtwii2c2-pinsHGPIO_28GPIO_29Mtwi2emmc-pinsXHGPIO_34GPIO_38GPIO_39GPIO_40GPIO_41GPIO_42GPIO_43GPIO_44GPIO_45GPIO_46GPIO_47MemmcV miim1-pinsHGPIO_56GPIO_57Mmiimmiim2-pinsHGPIO_58GPIO_59Mmiimmiim3-pinsHGPIO_52GPIO_53Mmiimi2cmux-pins HGPIO_35GPIO_36GPIO_50GPIO_51 Mtwi_scl_meSi2cmux-0-pinsHGPIO_35 Mtwi_scl_mpOi2cmux-1-pinsHGPIO_36 Mtwi_scl_mpPi2cmux-2-pinsHGPIO_50 Mtwi_scl_mpQi2cmux-3-pinsHGPIO_51 Mtwi_scl_mpRgpio@61101036c+microchip,sparx5-sgpio disabledlvdefault|switch nlgpio@0microchip,sparx5-sgpio-bankn 0` gpio@1microchip,sparx5-sgpio-bankn 0`gpio@611010484+microchip,sparx5-sgpiookaylvdefault|switch ngpio@0microchip,sparx5-sgpio-bankn 0@ gpio@1microchip,sparx5-sgpio-bankn 0@Tgpio@61101059c+microchip,sparx5-sgpiookaylvdefault|switch ngpio@0nmicrochip,sparx5-sgpio-bank 0` Wgpio@1microchip,sparx5-sgpio-bankn 0`Vi2c@600101000snps,designware-i2cokaylvdefault n+ ,Ni2c@600103000snps,designware-i2c disabledlvdefault n0+ ,tmon@610508110microchip,sparx5-temp nP mdio@6110102b0mscc,ocelot-miimokay+ n$ethernet-phy@0nethernet-phy@1nethernet-phy@2nethernet-phy@3nethernet-phy@4nethernet-phy@5nethernet-phy@6nethernet-phy@7n ethernet-phy@8n!ethernet-phy@9n "ethernet-phy@10n #ethernet-phy@11n $ethernet-phy@12n %ethernet-phy@13n &ethernet-phy@14n'ethernet-phy@15n(ethernet-phy@16n)ethernet-phy@17n*ethernet-phy@18n+ethernet-phy@19n,ethernet-phy@20n-ethernet-phy@21n.ethernet-phy@22n/ethernet-phy@23n0mdio@6110102d4mscc,ocelot-miimokaylvdefault+ n$ethernet-phy@24n1ethernet-phy@25n2ethernet-phy@26n3ethernet-phy@27n4ethernet-phy@28n5ethernet-phy@29n6ethernet-phy@30n7ethernet-phy@31n8ethernet-phy@32n9ethernet-phy@33n :ethernet-phy@34n ;ethernet-phy@35n <ethernet-phy@36n =ethernet-phy@37n >ethernet-phy@38n?ethernet-phy@39n@ethernet-phy@40nAethernet-phy@41nBethernet-phy@42nCethernet-phy@43nDethernet-phy@44nEethernet-phy@45nFethernet-phy@46nGethernet-phy@47nHmdio@6110102f8mscc,ocelot-miim disabledlvdefault+ n$mdio@61101031cmscc,ocelot-miimokaylvdefault+ n$ethernet-phy@64nMserdes@610808000microchip,sparx5-serdes n]switch@600000000microchip,sparx5-switch$n@@ Jcpudevgcb xtrfdmaptp$|switchethernet-ports+port@0n  qsgmiiport@1n  qsgmiiport@2n  qsgmiiport@3n  qsgmiiport@4n qsgmiiport@5n qsgmiiport@6n qsgmiiport@7n  qsgmiiport@8n !qsgmiiport@9n  "qsgmiiport@10n  #qsgmiiport@11n  $qsgmiiport@12n  %qsgmiiport@13n  &qsgmiiport@14n 'qsgmiiport@15n (qsgmiiport@16n )qsgmiiport@17n *qsgmiiport@18n +qsgmiiport@19n ,qsgmiiport@20n -qsgmiiport@21n .qsgmiiport@22n /qsgmiiport@23n 0qsgmiiport@24n 1qsgmiiport@25n 2qsgmiiport@26n 3qsgmiiport@27n 4qsgmiiport@28n 5qsgmiiport@29n 6qsgmiiport@30n 7qsgmiiport@31n 8qsgmiiport@32n  9qsgmiiport@33n! :qsgmiiport@34n" ;qsgmiiport@35n# <qsgmiiport@36n$ =qsgmiiport@37n% >qsgmiiport@38n& ?qsgmiiport@39n' @qsgmiiport@40n( Aqsgmiiport@41n) Bqsgmiiport@42n* Cqsgmiiport@43n+ Dqsgmiiport@44n, Eqsgmiiport@45n- Fqsgmiiport@46n. Gqsgmiiport@47n/ Hqsgmiiport@60n<a  10gbase-r%I)in-band-statusport@61n=a  10gbase-r%J)in-band-statusport@62n>a  10gbase-r%K)in-band-statusport@63n?a   10gbase-r%L)in-band-statusport@64n@ Msgmiigpio-restart gpio-restart  %1i2c-muxi2c-mux-pinctrl+:N)vi2c_sfp1i2c_sfp2i2c_sfp3i2c_sfp4idlelOEPOQYRcSi2c@0n+Ui2c@1n+Xi2c@2n+Yi2c@3n+Zleds gpio-ledsled-0 meth60:yellowTsoffled-1 meth60:greenTsoffled-2 meth61:yellowTsoffled-3 meth61:greenTsoffled-4 meth62:yellowTsoffled-5 meth62:greenTsoffled-6 meth63:yellowTsoffled-7 meth63:greenTsoffsfp-eth60sff,sfpUVVWWWIsfp-eth61sff,sfpXVVWWWJsfp-eth62sff,sfpYVVWWWKsfp-eth63sff,sfpZVVWWWLmemory@0bmemory n compatibleinterrupt-parent#address-cells#size-cellsmodelspi0serial0serial1stdout-pathcpudevice_typeregenable-methodnext-level-cachephandlecache-levelcache-unifiedinterruptsinterrupt-affinitystatus#clock-cellsclock-frequencyclocksranges#interrupt-cellsinterrupt-controller#mux-control-cellsmux-reg-masksreg-names#reset-cellscpu-sysconpinctrl-0pinctrl-namesreg-io-widthreg-shiftnum-csmux-controlsspi-max-frequencyclock-namesassigned-clocksassigned-clock-ratesbus-widthnon-removablemicrochip,clock-delaygpio-controller#gpio-cellsgpio-rangespinsfunctiondrive-strengthoutput-lowoutput-highresetsreset-namesngpiosmicrochip,sgpio-port-rangesi2c-sda-hold-time-ns#thermal-sensor-cells#phy-cellsinterrupt-namesmicrochip,bandwidthphysphy-handlephy-modesfpmanagedpriorityi2c-parentpinctrl-1pinctrl-2pinctrl-3pinctrl-4labeldefault-statei2c-bustx-disable-gpiosrate-select0-gpioslos-gpiosmod-def0-gpiostx-fault-gpios