Q8M(M)microchip,sparx5-pcb135microchip,sparx5 +%7Sparx5 PCB135 Reference Board (NAND)aliases=/axi@600000000/spi@600104000 B/axi@600000000/serial@600100000 J/axi@600000000/serial@600102000chosenRserial0:115200n8cpus+cpu-mapcluster0core0^core1^cpu@0arm,cortex-a53bcpun rspin-tablecpu@1arm,cortex-a53bcpun rspin-tablel2-cache0cachearm-pmuarm,cortex-a53-pmu psci arm,psci-0.2ysmc disabledtimerarm,armv8-timer0   lcpll-clk fixed-clockclock-controller@61110000cmicrochip,sparx5-dpll n $ahb-clk fixed-clock沀sys-clk fixed-clock%@@axi@600000000 simple-bus+interrupt-controller@600300000 arm,gic-v3+<n04  ! "   syscon@600000000.microchip,sparx5-cpu-sysconsysconsimple-mfd nmux-controller mmio-mux)< reset-controller@611010008microchip,sparx5-switch-reset nJgcbTaserial@600100000lvdefault ns16550a n  okayserial@600102000l vdefault ns16550a n  okayspi@600104000+microchip,sparx5-spi n@@ okayl vdefaultspi@0spi-mux +nflash@9jedec,spi-norzn spi@espi-mux +nflash@6 spi-nandl vdefaultnހtimer@600105000snps,dw-apb-timer nPtimer mmc@600800000microchip,dw-sparx5-sdhci disabled nl vdefaultcore/ pinctrl@6110101e0microchip,sparx5-pinctrlnP+@ cs1-pins7GPIO_16ethernet-phy@36n ?ethernet-phy@37n @ethernet-phy@38nAethernet-phy@39nBethernet-phy@40nCethernet-phy@41nDethernet-phy@42nEethernet-phy@43nFethernet-phy@44nGethernet-phy@45nHethernet-phy@46nIethernet-phy@47nJmdio@6110102f8mscc,ocelot-miim disabledlvdefault+ n$mdio@61101031cmscc,ocelot-miimokaylvdefault+ n$ethernet-phy@64nOserdes@610808000microchip,sparx5-serdes n]switch@600000000microchip,sparx5-switch$n@@ Jcpudevgcb xtrfdmaptp$\cswitchethernet-ports+port@0n qsgmiiport@1n qsgmiiport@2n qsgmiiport@3n qsgmiiport@4nqsgmiiport@5n qsgmiiport@6n!qsgmiiport@7n"qsgmiiport@8n#qsgmiiport@9n $qsgmiiport@10n %qsgmiiport@11n &qsgmiiport@12n 'qsgmiiport@13n (qsgmiiport@14n)qsgmiiport@15n*qsgmiiport@16n+qsgmiiport@17n,qsgmiiport@18n-qsgmiiport@19n.qsgmiiport@20n/qsgmiiport@21n0qsgmiiport@22n1qsgmiiport@23n2qsgmiiport@24n3qsgmiiport@25n4qsgmiiport@26n5qsgmiiport@27n6qsgmiiport@28n7qsgmiiport@29n8qsgmiiport@30n9qsgmiiport@31n:qsgmiiport@32n ;qsgmiiport@33n!<qsgmiiport@34n"=qsgmiiport@35n#>qsgmiiport@36n$?qsgmiiport@37n%@qsgmiiport@38n&Aqsgmiiport@39n'Bqsgmiiport@40n(Cqsgmiiport@41n)Dqsgmiiport@42n*Eqsgmiiport@43n+Fqsgmiiport@44n,Gqsgmiiport@45n-Hqsgmiiport@46n.Iqsgmiiport@47n/Jqsgmiiport@60n<a 10gbase-rK in-band-statusport@61n=a 10gbase-rL in-band-statusport@62n>a 10gbase-rM in-band-statusport@63n?a  10gbase-rN in-band-statusport@64n@Osgmiigpio-restart gpio-restart p%i2c-muxi2c-mux-pinctrl+P)vi2c_sfp1i2c_sfp2i2c_sfp3i2c_sfp4idlelQ%R/S9TCUi2c@0n+Wi2c@1n+Zi2c@2n+[i2c@3n+\leds gpio-ledsled-0 Meth60:yellowpVSoffled-1 Meth60:greenpVSoffled-2 Meth61:yellowpVSoffled-3 Meth61:greenpVSoffled-4 Meth62:yellowpVSoffled-5 Meth62:greenpVSoffled-6 Meth63:yellowpVSoffled-7 Meth63:greenpVSoffsfp-eth60sff,sfpaWiXzXYYYKsfp-eth61sff,sfpaZiXzXYYYLsfp-eth62sff,sfpa[iXzXYYYMsfp-eth63sff,sfpa\iXzXYYYNmemory@0bmemory n compatibleinterrupt-parent#address-cells#size-cellsmodelspi0serial0serial1stdout-pathcpudevice_typeregenable-methodnext-level-cachephandlecache-levelcache-unifiedinterruptsinterrupt-affinitystatus#clock-cellsclock-frequencyclocksranges#interrupt-cellsinterrupt-controller#mux-control-cellsmux-reg-masksreg-names#reset-cellscpu-sysconpinctrl-0pinctrl-namesreg-io-widthreg-shiftnum-csmux-controlsspi-max-frequencyrx-sample-delay-nsclock-namesassigned-clocksassigned-clock-ratesbus-widthgpio-controller#gpio-cellsgpio-rangespinsfunctionoutput-lowoutput-highresetsreset-namesngpiosmicrochip,sgpio-port-rangesi2c-sda-hold-time-ns#thermal-sensor-cells#phy-cellsinterrupt-namesmicrochip,bandwidthphysphy-handlephy-modesfpmanagedpriorityi2c-parentpinctrl-1pinctrl-2pinctrl-3pinctrl-4labeldefault-statei2c-bustx-disable-gpiosrate-select0-gpioslos-gpiosmod-def0-gpiostx-fault-gpios