Ð þí^a8Z$(=Yì)microchip,sparx5-pcb134microchip,sparx5 +-7Sparx5 PCB134 Reference Board (eMMC enabled)aliases=/axi@600000000/spi@600104000 B/axi@600000000/serial@600100000 J/axi@600000000/serial@600102000chosenRserial0:115200n8cpus+cpu-mapcluster0core0^core1^cpu@0arm,cortex-a53bcpun rspin-table€‘cpu@1arm,cortex-a53bcpun rspin-table€‘l2-cache0cache™¥‘arm-pmuarm,cortex-a53-pmu ³¾psci arm,psci-0.2ysmc Ñdisabledtimerarm,armv8-timer0³   lcpll-clk fixed-clockØå•ù‘clock-controller@61110000cmicrochip,sparx5-dpllØõ n $‘ ahb-clk fixed-clockØåæ²€‘sys-clk fixed-clockØå%@¾@‘axi@600000000 simple-bus+üinterrupt-controller@600300000 arm,gic-v3+<n04  ! "  ³ ‘syscon@600000000.microchip,sparx5-cpu-sysconsysconsimple-mfd nБmux-controller mmio-mux)<ˆð‘ reset-controller@611010008microchip,sparx5-switch-reset nJgcbTa‘serial@600100000lvdefault ns16550a n õ„‘ ³ Ñokayserial@600102000l vdefault ns16550a n õ„‘ ³ Ñokayspi@600104000+microchip,sparx5-spi n@@›„‘õ ³ Ñokayspi@0spi-mux¢ +nflash@9jedec,spi-nor¯zn timer@600105000snps,dw-apb-timer nPõÁtimer ³mmc@600800000microchip,dw-sparx5-sdhciÑokay n€l vdefaultõ ÁcoreÍ Ý/¯ ³òü³u pinctrl@6110101e0microchip,sparx5-pinctrlnàP€ 0< @ ³‘ cs1-pinsHGPIO_16Msics2-pinsHGPIO_17Msics3-pinsHGPIO_18Msisi2-pinsHGPIO_39GPIO_40GPIO_41Msi2sgpio-pinsHGPIO_0GPIO_1GPIO_2GPIO_3Msg0‘sgpio1-pinsHGPIO_4GPIO_5GPIO_12GPIO_13Msg1‘sgpio2-pins HGPIO_30GPIO_31GPIO_32GPIO_33Msg2‘uart-pinsHGPIO_10GPIO_11Muart‘uart2-pinsHGPIO_26GPIO_27Muart2‘ i2c-pinsHGPIO_14GPIO_15Mtwi‘i2c2-pinsHGPIO_28GPIO_29Mtwi2‘emmc-pinsXHGPIO_34GPIO_38GPIO_39GPIO_40GPIO_41GPIO_42GPIO_43GPIO_44GPIO_45GPIO_46GPIO_47MemmcV‘ miim1-pinsHGPIO_56GPIO_57Mmiim‘miim2-pinsHGPIO_58GPIO_59Mmiim‘miim3-pinsHGPIO_52GPIO_53Mmiim‘i2cmux-pins`HGPIO_16GPIO_17GPIO_18GPIO_19GPIO_20GPIO_22GPIO_36GPIO_35GPIO_50GPIO_51GPIO_56GPIO_57 Mtwi_scl_me‘;i2cmux-0-pinsHGPIO_16 Mtwi_scl_mp‘/i2cmux-1-pinsHGPIO_17 Mtwi_scl_mp‘0i2cmux-2-pinsHGPIO_18 Mtwi_scl_mp‘1i2cmux-3-pinsHGPIO_19 Mtwi_scl_mp‘2i2cmux-4-pinsHGPIO_20 Mtwi_scl_mp‘3i2cmux-5-pinsHGPIO_22 Mtwi_scl_mp‘4i2cmux-6-pinsHGPIO_36 Mtwi_scl_mp‘5i2cmux-7-pinsHGPIO_35 Mtwi_scl_mp‘6i2cmux-8-pinsHGPIO_50 Mtwi_scl_mp‘7i2cmux-9-pinsHGPIO_51 Mtwi_scl_mp‘8i2cmux-10-pinsHGPIO_56 Mtwi_scl_mp‘9i2cmux-11-pinsHGPIO_57 Mtwi_scl_mp‘:gpio@61101036c+microchip,sparx5-sgpioÑokayõlvdefault|ƒswitch nlgpio@0microchip,sparx5-sgpio-bankn 0«@ ³gpio@1microchip,sparx5-sgpio-bankn 0«@‘<gpio@611010484+microchip,sparx5-sgpioÑokayõlvdefault|ƒswitch n„gpio@0microchip,sparx5-sgpio-bankn 0«@ ³gpio@1microchip,sparx5-sgpio-bankn 0«@‘=gpio@61101059c+microchip,sparx5-sgpioÑokayõlvdefault|ƒswitch nœ gpio@0nmicrochip,sparx5-sgpio-bank 0«` ³‘@gpio@1microchip,sparx5-sgpio-bankn 0«`‘?i2c@600101000snps,designware-i2cÑokaylvdefault n+ ³ ²,冠õ‘.i2c@600103000snps,designware-i2c Ñdisabledlvdefault n0+ ³ ²,冠õtmon@610508110microchip,sparx5-temp nP Çõmdio@6110102b0mscc,ocelot-miim Ñdisabled+ n°$mdio@6110102d4mscc,ocelot-miim Ñdisabledlvdefault+ nÔ$mdio@6110102f8mscc,ocelot-miim Ñdisabledlvdefault+ nø$mdio@61101031cmscc,ocelot-miimÑokaylvdefault+ n$ethernet-phy@64n‘-serdes@610808000microchip,sparx5-serdesÝõ n€€]‘switch@600000000microchip,sparx5-switch$n@@À¯ Jcpudevgcb èxtrfdmaptp$³|ƒswitchethernet-ports+port@12n ø'   10gbase-r-1in-band-statusport@13n ø'  10gbase-r11in-band-statusport@14nø'  10gbase-r51in-band-statusport@15nø'  10gbase-r91in-band-statusport@48n0ø'  10gbase-r=1in-band-statusport@49n1ø'  10gbase-rA1in-band-statusport@50n2ø'  10gbase-rE1in-band-statusport@51n3ø'  10gbase-r I1in-band-statusport@52n4ø'  10gbase-r!M1in-band-statusport@53n5ø'  10gbase-r"Q1in-band-statusport@54n6ø'  10gbase-r#U1in-band-statusport@55n7ø'  10gbase-r$Y1in-band-statusport@56n8ø'  10gbase-r%]1in-band-statusport@57n9ø'  10gbase-r&a1in-band-statusport@58n:ø'  10gbase-r'e1in-band-statusport@59n;ø'  10gbase-r(i1in-band-statusport@60n<ø'  10gbase-r)m1in-band-statusport@61n=ø'  10gbase-r*q1in-band-statusport@62n>ø'  10gbase-r+u1in-band-statusport@63n?ø'   10gbase-r,y1in-band-statusport@64n@øè 9-sgmiigpio-restart gpio-restart ¬ %DÈi2c-mux-0i2c-mux-pinctrl+M.tvi2c_sfp1i2c_sfp2i2c_sfp3i2c_sfp4i2c_sfp5i2c_sfp6i2c_sfp7i2c_sfp8i2c_sfp9i2c_sfp10i2c_sfp11i2c_sfp12idlel/X0b1l2v3€4Š5”6ž7¨8²9½:È;i2c@0n+‘>i2c@1n+‘Ai2c@2n+‘Bi2c@3n+‘Ci2c@4n+‘Di2c@5n+‘Ei2c@6n+‘Fi2c@7n+‘Gi2c@8n+‘Hi2c@9n +‘Ii2c@an +‘Ji2c@bn +‘Ki2c-mux-1 i2c-mux-gpio+M.0Ó 7 < = 6Ýi2c@0n+‘Li2c@1n+‘Mi2c@2n+‘Ni2c@3n+‘Oi2c@4n+‘Pi2c@5n+‘Qi2c@6n+‘Ri2c@7n+‘Sleds gpio-ledsled-0 ètwr0:green¬<led-1 ètwr0:yellow¬<led-2 ètwr1:green¬< led-3 ètwr1:yellow¬< led-4 ètwr2:green¬< led-5 ètwr2:yellow¬< led-6 ètwr3:green¬< led-7 ètwr3:yellow¬< led-8 èeth12:green¬< îoffled-9 èeth12:yellow¬< îoffled-10 èeth13:green¬< îoffled-11 èeth13:yellow¬< îoffled-12 èeth14:green¬<îoffled-13 èeth14:yellow¬<îoffled-14 èeth15:green¬<îoffled-15 èeth15:yellow¬<îoffled-16 èeth48:green¬=îoffled-17 èeth48:yellow¬=îoffled-18 èeth49:green¬=îoffled-19 èeth49:yellow¬=îoffled-20 èeth50:green¬=îoffled-21 èeth50:yellow¬=îoffled-22 èeth51:green¬=îoffled-23 èeth51:yellow¬=îoffled-24 èeth52:green¬=îoffled-25 èeth52:yellow¬=îoffled-26 èeth53:green¬=îoffled-27 èeth53:yellow¬=îoffled-28 èeth54:green¬=îoffled-29 èeth54:yellow¬=îoffled-30 èeth55:green¬=îoffled-31 èeth55:yellow¬=îoffled-32 èeth56:green¬=îoffled-33 èeth56:yellow¬=îoffled-34 èeth57:green¬=îoffled-35 èeth57:yellow¬=îoffled-36 èeth58:green¬=îoffled-37 èeth58:yellow¬=îoffled-38 èeth59:green¬=îoffled-39 èeth59:yellow¬=îoffled-40 èeth60:green¬=îoffled-41 èeth60:yellow¬=îoffled-42 èeth61:green¬=îoffled-43 èeth61:yellow¬=îoffled-44 èeth62:green¬=îoffled-45 èeth62:yellow¬=îoffled-46 èeth63:green¬=îoffled-47 èeth63:yellow¬=îoffsfp-eth12sff,sfpü>? @ @ .@ ‘sfp-eth13sff,sfpüA? @ @ .@ ‘sfp-eth14sff,sfpüB? @ @ .@‘sfp-eth15sff,sfpüC?@@.@‘sfp-eth48sff,sfpüD?@@.@‘sfp-eth49sff,sfpüE?@@.@‘sfp-eth50sff,sfpüF?@@.@‘sfp-eth51sff,sfpüG?@@.@‘ sfp-eth52sff,sfpüH?@@.@‘!sfp-eth53sff,sfpüI?@@.@‘"sfp-eth54sff,sfpüJ?@@.@‘#sfp-eth55sff,sfpüK?@@.@‘$sfp-eth56sff,sfpüL?@@.@‘%sfp-eth57sff,sfpüM?@@.@‘&sfp-eth58sff,sfpüN?@@.@‘'sfp-eth59sff,sfpüO?@@.@‘(sfp-eth60sff,sfpüP?@@.@‘)sfp-eth61sff,sfpüQ?@@.@‘*sfp-eth62sff,sfpüR?@@.@‘+sfp-eth63sff,sfpüS?@@.@‘,memory@0bmemory n compatibleinterrupt-parent#address-cells#size-cellsmodelspi0serial0serial1stdout-pathcpudevice_typeregenable-methodnext-level-cachephandlecache-levelcache-unifiedinterruptsinterrupt-affinitystatus#clock-cellsclock-frequencyclocksranges#interrupt-cellsinterrupt-controller#mux-control-cellsmux-reg-masksreg-names#reset-cellscpu-sysconpinctrl-0pinctrl-namesreg-io-widthreg-shiftnum-csmux-controlsspi-max-frequencyclock-namesassigned-clocksassigned-clock-ratesbus-widthnon-removablemicrochip,clock-delaygpio-controller#gpio-cellsgpio-rangespinsfunctiondrive-strengthoutput-lowoutput-highresetsreset-namesmicrochip,sgpio-port-rangesngpiosi2c-sda-hold-time-ns#thermal-sensor-cells#phy-cellsinterrupt-namesmicrochip,bandwidthphysphy-modesfpmicrochip,sd-sgpiomanagedphy-handlepriorityi2c-parentpinctrl-1pinctrl-2pinctrl-3pinctrl-4pinctrl-5pinctrl-6pinctrl-7pinctrl-8pinctrl-9pinctrl-10pinctrl-11pinctrl-12mux-gpiosidle-statelabeldefault-statei2c-bustx-disable-gpioslos-gpiosmod-def0-gpiostx-fault-gpios