_u8[X([ )microchip,sparx5-pcb134microchip,sparx5 +%7Sparx5 PCB134 Reference Board (NAND)aliases=/axi@600000000/spi@600104000 B/axi@600000000/serial@600100000 J/axi@600000000/serial@600102000chosenRserial0:115200n8cpus+cpu-mapcluster0core0^core1^cpu@0arm,cortex-a53bcpun rspin-tablecpu@1arm,cortex-a53bcpun rspin-tablel2-cache0cachearm-pmuarm,cortex-a53-pmu psci arm,psci-0.2ysmc disabledtimerarm,armv8-timer0   lcpll-clk fixed-clockclock-controller@61110000cmicrochip,sparx5-dpll n $ahb-clk fixed-clock沀sys-clk fixed-clock%@@axi@600000000 simple-bus+interrupt-controller@600300000 arm,gic-v3+<n04  ! "   syscon@600000000.microchip,sparx5-cpu-sysconsysconsimple-mfd nmux-controller mmio-mux)< reset-controller@611010008microchip,sparx5-switch-reset nJgcbTaserial@600100000lvdefault ns16550a n  okayserial@600102000l vdefault ns16550a n  okayspi@600104000+microchip,sparx5-spi n@@ okayl vdefaultspi@0spi-mux +nflash@9jedec,spi-norzn spi@espi-mux +nflash@6 spi-nandl vdefaultnހtimer@600105000snps,dw-apb-timer nPtimer mmc@600800000microchip,dw-sparx5-sdhci disabled nl vdefaultcore/ pinctrl@6110101e0microchip,sparx5-pinctrlnP+@ cs1-pins7GPIO_16gpio@611010484+microchip,sparx5-sgpiookaylvdefault\cswitch nogpio@0microchip,sparx5-sgpio-bankn@ gpio@1microchip,sparx5-sgpio-bankn@?gpio@61101059c+microchip,sparx5-sgpiookaylvdefault\cswitch no gpio@0nmicrochip,sparx5-sgpio-bank` Bgpio@1microchip,sparx5-sgpio-bankn`Ai2c@600101000snps,designware-i2cokaylvdefault n+ ,0i2c@600103000snps,designware-i2c disabledlvdefault n0+ ,tmon@610508110microchip,sparx5-temp nP mdio@6110102b0mscc,ocelot-miim disabled+ n$mdio@6110102d4mscc,ocelot-miim disabledlvdefault+ n$mdio@6110102f8mscc,ocelot-miim disabledlvdefault+ n$mdio@61101031cmscc,ocelot-miimokaylvdefault+ n$ethernet-phy@64n/serdes@610808000microchip,sparx5-serdes n]switch@600000000microchip,sparx5-switch$n@@ Jcpudevgcb xtrfdmaptp$\cswitchethernet-ports+port@12n '  10gbase-r-in-band-statusport@13n ' 10gbase-r1in-band-statusport@14n' 10gbase-r5in-band-statusport@15n' 10gbase-r9in-band-statusport@48n0' 10gbase-r=in-band-statusport@49n1' 10gbase-r Ain-band-statusport@50n2' 10gbase-r!Ein-band-statusport@51n3' 10gbase-r"Iin-band-statusport@52n4' 10gbase-r#Min-band-statusport@53n5' 10gbase-r$Qin-band-statusport@54n6' 10gbase-r%Uin-band-statusport@55n7' 10gbase-r&Yin-band-statusport@56n8' 10gbase-r']in-band-statusport@57n9' 10gbase-r(ain-band-statusport@58n:' 10gbase-r)ein-band-statusport@59n;' 10gbase-r*iin-band-statusport@60n<' 10gbase-r+min-band-statusport@61n=' 10gbase-r,qin-band-statusport@62n>' 10gbase-r-uin-band-statusport@63n?'  10gbase-r.yin-band-statusport@64n@/sgmiigpio-restart gpio-restart %$i2c-mux-0i2c-mux-pinctrl+-0tvi2c_sfp1i2c_sfp2i2c_sfp3i2c_sfp4i2c_sfp5i2c_sfp6i2c_sfp7i2c_sfp8i2c_sfp9i2c_sfp10i2c_sfp11i2c_sfp12idlel182B3L4V5`6j7t8~9:;<=i2c@0n+@i2c@1n+Ci2c@2n+Di2c@3n+Ei2c@4n+Fi2c@5n+Gi2c@6n+Hi2c@7n+Ii2c@8n+Ji2c@9n +Ki2c@an +Li2c@bn +Mi2c-mux-1 i2c-mux-gpio+-007<=6i2c@0n+Ni2c@1n+Oi2c@2n+Pi2c@3n+Qi2c@4n+Ri2c@5n+Si2c@6n+Ti2c@7n+Uleds gpio-ledsled-0 twr0:green>led-1 twr0:yellow>led-2 twr1:green> led-3 twr1:yellow> led-4 twr2:green> led-5 twr2:yellow> led-6 twr3:green> led-7 twr3:yellow> led-8 eth12:green> offled-9 eth12:yellow> offled-10 eth13:green> offled-11 eth13:yellow> offled-12 eth14:green>offled-13 eth14:yellow>offled-14 eth15:green>offled-15 eth15:yellow>offled-16 eth48:green?offled-17 eth48:yellow?offled-18 eth49:green?offled-19 eth49:yellow?offled-20 eth50:green?offled-21 eth50:yellow?offled-22 eth51:green?offled-23 eth51:yellow?offled-24 eth52:green?offled-25 eth52:yellow?offled-26 eth53:green?offled-27 eth53:yellow?offled-28 eth54:green?offled-29 eth54:yellow?offled-30 eth55:green?offled-31 eth55:yellow?offled-32 eth56:green?offled-33 eth56:yellow?offled-34 eth57:green?offled-35 eth57:yellow?offled-36 eth58:green?offled-37 eth58:yellow?offled-38 eth59:green?offled-39 eth59:yellow?offled-40 eth60:green?offled-41 eth60:yellow?offled-42 eth61:green?offled-43 eth61:yellow?offled-44 eth62:green?offled-45 eth62:yellow?offled-46 eth63:green?offled-47 eth63:yellow?offsfp-eth12sff,sfp@A B B B sfp-eth13sff,sfpCA B B B sfp-eth14sff,sfpDA B B Bsfp-eth15sff,sfpEABBBsfp-eth48sff,sfpFABBBsfp-eth49sff,sfpGABBB sfp-eth50sff,sfpHABBB!sfp-eth51sff,sfpIABBB"sfp-eth52sff,sfpJABBB#sfp-eth53sff,sfpKABBB$sfp-eth54sff,sfpLABBB%sfp-eth55sff,sfpMABBB&sfp-eth56sff,sfpNABBB'sfp-eth57sff,sfpOABBB(sfp-eth58sff,sfpPABBB)sfp-eth59sff,sfpQABBB*sfp-eth60sff,sfpRABBB+sfp-eth61sff,sfpSABBB,sfp-eth62sff,sfpTABBB-sfp-eth63sff,sfpUABBB.memory@0bmemory n compatibleinterrupt-parent#address-cells#size-cellsmodelspi0serial0serial1stdout-pathcpudevice_typeregenable-methodnext-level-cachephandlecache-levelcache-unifiedinterruptsinterrupt-affinitystatus#clock-cellsclock-frequencyclocksranges#interrupt-cellsinterrupt-controller#mux-control-cellsmux-reg-masksreg-names#reset-cellscpu-sysconpinctrl-0pinctrl-namesreg-io-widthreg-shiftnum-csmux-controlsspi-max-frequencyrx-sample-delay-nsclock-namesassigned-clocksassigned-clock-ratesbus-widthgpio-controller#gpio-cellsgpio-rangespinsfunctionoutput-lowoutput-highresetsreset-namesmicrochip,sgpio-port-rangesngpiosi2c-sda-hold-time-ns#thermal-sensor-cells#phy-cellsinterrupt-namesmicrochip,bandwidthphysphy-modesfpmicrochip,sd-sgpiomanagedphy-handlepriorityi2c-parentpinctrl-1pinctrl-2pinctrl-3pinctrl-4pinctrl-5pinctrl-6pinctrl-7pinctrl-8pinctrl-9pinctrl-10pinctrl-11pinctrl-12mux-gpiosidle-statelabeldefault-statei2c-bustx-disable-gpioslos-gpiosmod-def0-gpiostx-fault-gpios