8x(@lge,lg1312-reflge,lg1312&/7LG Electronics, DTV SoC LG1312 Reference Boardcpuscpu@0=cpuarm,cortex-a53IM^cpu@1=cpuarm,cortex-a53IfpsciM^cpu@2=cpuarm,cortex-a53IfpsciM^cpu@3=cpuarm,cortex-a53IfpsciM^l2-cache0cachet^psciarm,psci-0.2arm,pscimsmcinterrupt-controller@c0001000 arm,gic-4000I @ ` ^pmuarm,cortex-a53-pmu0timerarm,armv8-timer0   clk_bus fixed-clock = BUSCLK^soc simple-bus&ethernet@c1b00000 cdns,gem I $ +hclkpclk7rmii@amba simple-bus&timer@fd100000arm,sp804arm,primecell I  $+timer0clktimer1clkapb_pclkwatchdog@fd200000arm,sp805arm,primecell I  $+wdog_clkapb_pclkserial@fe000000arm,pl011arm,primecell I $ +apb_pclkLokayserial@fe100000arm,pl011arm,primecell I $ +apb_pclk Ldisabledserial@fe200000arm,pl011arm,primecell I  $ +apb_pclk Ldisabledspi@fe800000arm,pl022arm,primecell I $ +apb_pclkspi@fe900000arm,pl022arm,primecell I $ +apb_pclkdma-controller@c1128000arm,pl330arm,primecell I $ +apb_pclkSgpio@fd400000^arm,pl061arm,primecellj I@$ +apb_pclk Ldisabledgpio@fd410000^arm,pl061arm,primecellj IA$ +apb_pclk Ldisabledgpio@fd420000^arm,pl061arm,primecellj IB$ +apb_pclk Ldisabledgpio@fd430000^arm,pl061arm,primecellj IC$ +apb_pclkgpio@fd440000^arm,pl061arm,primecellj ID$ +apb_pclk Ldisabledgpio@fd450000^arm,pl061arm,primecellj IE$ +apb_pclk Ldisabledgpio@fd460000^arm,pl061arm,primecellj IF$ +apb_pclk Ldisabledgpio@fd470000^arm,pl061arm,primecellj IG$ +apb_pclk Ldisabledgpio@fd480000^arm,pl061arm,primecellj IH$ +apb_pclk Ldisabledgpio@fd490000^arm,pl061arm,primecellj II$ +apb_pclk Ldisabledgpio@fd4a0000^arm,pl061arm,primecellj IJ$ +apb_pclk Ldisabledgpio@fd4b0000^arm,pl061arm,primecellj IK$ +apb_pclkgpio@fd4c0000^arm,pl061arm,primecellj IL$ +apb_pclk Ldisabledgpio@fd4d0000^arm,pl061arm,primecellj IM$ +apb_pclk Ldisabledgpio@fd4e0000^arm,pl061arm,primecellj IN$ +apb_pclk Ldisabledgpio@fd4f0000^arm,pl061arm,primecellj IO$ +apb_pclk Ldisabledgpio@fd500000^arm,pl061arm,primecellj IP$ +apb_pclk Ldisabledgpio@fd510000^arm,pl061arm,primecellj IQ$ +apb_pclkaliasesz/amba/serial@fe000000/amba/serial@fe100000/amba/serial@fe200000memory@0=memory I chosenserial0:115200n8 #address-cells#size-cellscompatibleinterrupt-parentmodeldevice_typeregnext-level-cachephandleenable-methodcache-levelcache-unifiedcpu_suspendcpu_offcpu_on#interrupt-cellsinterrupt-controllerinterruptsinterrupt-affinity#clock-cellsclock-frequencyclock-output-namesrangesclocksclock-namesphy-modemac-addressstatus#dma-cells#gpio-cellsgpio-controllerserial0serial1serial2stdout-path