28/l(/40intel,socfpga-agilex-n6000intel,socfpga-agilex &SoCFPGA Agilex n6000reserved-memory ,svcbuffer@0shared-dma-pool37AHcpus cpu@0arm,cortex-a53Pcpu\psci3Hcpu@1arm,cortex-a53Pcpu\psci3Hcpu@2arm,cortex-a53Pcpu\psci3Hcpu@3arm,cortex-a53Pcpu\psci3Hfirmwaresvcintel,agilex-svccsmcjfpga-mgrintel,agilex-soc-fpga-mgr xdisabledHfpga-region fpga-region pmuarm,cortex-a53-pmu0psci arm,psci-0.2csmcinterrupt-controller@fffc1000arm,gic-400arm,cortex-a15-gic@3 @ ` Hclockscb-intosc-hs-div2-clk fixed-clockcb-intosc-ls-clk fixed-clockf2s-free-clk fixed-clockosc1 fixed-clock}x@qspi-clk fixed-clock Htimerarm,armv8-timer0   usbphyusb-nop-xceivH soc@0  simple-busPsoc,clock-controller@ffd10000intel,agilex-clkmgr3H ethernet@ff8000008altr,socfpga-stmmac-a10-s10snps,dwmac-3.74asnps,dwmac3  Zmacirq! ((stmmacethahb4@B@Pk  r D ) -stmmacethptp_ref xdisabledHethernet@ff8020008altr,socfpga-stmmac-a10-s10snps,dwmac-3.74asnps,dwmac3  [macirq!!)(stmmacethahb4@B@Pk  r H + -stmmacethptp_ref xdisabledethernet@ff8040008altr,socfpga-stmmac-a10-s10snps,dwmac-3.74asnps,dwmac3@  \macirq!"*(stmmacethahb4@B@Pk  r L , -stmmacethptp_ref xdisabledgpio@ffc03200 snps,dw-apb-gpio32!X xdisabledgpio-controller@0snps,dw-apb-gpio-port3 ngpio@ffc03300 snps,dw-apb-gpio33!Y xdisabledgpio-controller@0snps,dw-apb-gpio-port3 oi2c@ffc02800 snps,designware-i2c3( g!H # xdisabledi2c@ffc02900 snps,designware-i2c3) h!I # xdisabledi2c@ffc02a00 snps,designware-i2c3* i!J # xdisabledi2c@ffc02b00 snps,designware-i2c3+ j!K # xdisabledi2c@ffc02c00 snps,designware-i2c3, k!L # xdisabledmmc@ff808000 altr,socfpga-dw-mshc3 `7!'(reset " 2biuciuk  r ( xdisabledHnand-controller@ffb90000 altr,socfpga-denali-nand3nand_datadenali_reg a / 5 6nandnand_xecc!%- xdisabledsram@ffe00000 mmio-sram3  ,Hdma-controller@ffda0000arm,pl330arm,primecell3lQRSTUVWXY!05 (dmadma-ocp ! apb_pclkpinctrl@ffd13000pinctrl-single30 pinctrl@ffd13100pinctrl-single31  rstmgr@ffd11000$altr,stratix10-rst-mgraltr,rst-mgr3!Hiommu@fa000000arm,mmu-500arm,smmu-v23.AN   ! xdisabledH spi@ffda4000snps,dw-apb-ssi 3@ c!1(spi`m ! xdisabledspi@ffda5000snps,dw-apb-ssi 3P d!2(spi`m ! xdisabledsysmgr@ffd12000altr,sys-mgr-s10altr,sys-mgr3 H timer0@ffc03000snps,dw-apb-timer q30 #timertimer1@ffc03100snps,dw-apb-timer r31 #timertimer2@ffd00000snps,dw-apb-timer s3 #timertimer3@ffd00100snps,dw-apb-timer t3 #timerserial@ffc02000snps,dw-apb-uart3  lt`!Pxokay #serial@ffc02100snps,dw-apb-uart3! mt`!Q #xokayusb@ffb00000%intel,socfpga-agilex-hsotgsnps,dwc23 ]~  usb2-phy!#+(dwc2dwc2-ecc 4otgk  xdisabledHusb@ffb40000%intel,socfpga-agilex-hsotgsnps,dwc23 ^~  usb2-phy!$,(dwc2dwc2-ecck  4 xdisabledwatchdog@ffd00200 snps,dw-wdt3 u!@ xokaywatchdog@ffd00300 snps,dw-wdt3 v!A  xdisabledwatchdog@ffd00400 snps,dw-wdt3 }!B  xdisabledwatchdog@ffd00500 snps,dw-wdt3 ~!C  xdisabledsdr@f8011100altr,sdr-ctlsyscon3H eccmgr:altr,socfpga-s10-ecc-manageraltr,socfpga-a10-ecc-managerr   ,sdramedacaltr,sdram-edac-s10 ocram-ecc@ff8cc0006altr,socfpga-s10-ocram-eccaltr,socfpga-a10-ocram-ecc3usb0-ecc@ff8c4000.altr,socfpga-s10-usb-eccaltr,socfpga-usb-ecc3@emac0-rx-ecc@ff8c00006altr,socfpga-s10-eth-mac-eccaltr,socfpga-eth-mac-ecc3emac0-tx-ecc@ff8c04006altr,socfpga-s10-eth-mac-eccaltr,socfpga-eth-mac-ecc3sdmmca-ecc@ff8c8c002altr,socfpga-s10-sdmmc-eccaltr,socfpga-sdmmc-ecc3spi@ff8d2000!intel,socfpga-qspicdns,qspi-nor 3   xdisabledbus@80000000 simple-bus3`axi_h2faxi_h2f_lw ,dma-controller@0intel,hps-copy-engine 3aliases/soc@0/serial@ffc02100/soc@0/serial@ffc02000/soc@0/ethernet@ff800000/soc@0/ethernet@ff802000/soc@0/ethernet@ff804000chosenserial0:115200n8memory@80000000Pmemory3 compatible#address-cells#size-cellsmodelrangesregalignmentno-mapphandledevice_typeenable-methodmemory-regionstatusfpga-mgrinterruptsinterrupt-affinityinterrupt-parent#interrupt-cellsinterrupt-controller#clock-cellsclock-frequency#phy-cellsinterrupt-namesmac-addressresetsreset-namestx-fifo-depthrx-fifo-depthsnps,multicast-filter-binsiommusaltr,sysmgr-sysconclocksclock-namesgpio-controller#gpio-cellssnps,nr-gpiosreg-names#dma-cells#pinctrl-cellspinctrl-single,register-widthpinctrl-single,function-mask#reset-cells#global-interrupts#iommu-cellsstream-match-maskreg-io-widthnum-csreg-shiftphysphy-namesaltr,sdr-sysconaltr,ecc-parentcdns,fifo-depthcdns,fifo-widthcdns,trigger-addressserial0serial1ethernet0ethernet1ethernet2stdout-path