48/( /3altr,socfpga-stratix10-swvpaltr,socfpga-stratix10 &SOCFPGA Stratix 10 SWVPreserved-memory ,svcbuffer@0shared-dma-pool37AHcpus cpu@0arm,cortex-a53Pcpu \spin-tablej3{Hcpu@1arm,cortex-a53Pcpu \spin-tablej3{Hcpu@2arm,cortex-a53Pcpu \spin-tablej3{Hcpu@3arm,cortex-a53Pcpu \spin-tablej3{HcachecacheHfirmwaresvcintel,stratix10-svccsmcfpga-mgrintel,stratix10-soc-fpga-mgrHfpga-region fpga-region pmuarm,cortex-a53-pmu0psci arm,psci-0.2csmctimerarm,armv8-timer0   interrupt-controller@fffc1000arm,gic-400arm,cortex-a15-gic@3 @ ` Hclockscb-intosc-hs-div2-clk fixed-clockcb-intosc-ls-clk fixed-clockf2s-free-clk fixed-clockosc1 fixed-clock}x@qspi-clk fixed-clock Hsoc@0  simple-busPsoc,clock-controller@ffd10000intel,stratix10-clkmgr3H ethernet@ff8000008altr,socfpga-stmmac-a10-s10snps,dwmac-3.74asnps,dwmac3  Z/macirq?K (Rstmmacethahb^ 4 7estmmacethptp_refq@@   DokayrgmiiHethernet@ff8020008altr,socfpga-stmmac-a10-s10snps,dwmac-3.74asnps,dwmac3  [/macirq?K ! )Rstmmacethahb^ 5 7estmmacethptp_refq@@   Hokayrgmiiethernet@ff8040008altr,socfpga-stmmac-a10-s10snps,dwmac-3.74asnps,dwmac3@  \/macirq?K " *Rstmmacethahb^ 6 7estmmacethptp_refq@@   Lokayrgmiigpio@ffc03200 snps,dw-apb-gpio32K X disabledgpio-controller@0snps,dw-apb-gpio-port3 ngpio@ffc03300 snps,dw-apb-gpio33K Y disabledgpio-controller@0snps,dw-apb-gpio-port3 oi2c@ffc02800 snps,designware-i2c3( gK H^ - disabledi2c@ffc02900 snps,designware-i2c3) hK I^ - disabledi2c@ffc02a00 snps,designware-i2c3* iK J^ - disabledi2c@ffc02b00 snps,designware-i2c3+ jK K^ - disabledi2c@ffc02c00 snps,designware-i2c3, kK L^ - disabledmmc@ff808000 altr,socfpga-dw-mshc3 `tK 'Rreset^ , 9ebiuciu   (okay .8nand-controller@ffb90000 altr,socfpga-denali-nand3Bnand_datadenali_reg a^ = > ?enandnand_xeccK % - disabledsram@ffe00000 mmio-sram3  ,Hdma-controller@ffda0000arm,pl330arm,primecell3lQRSTUVWXYL^ + eapb_pclkK 0 5 Rdmadma-ocppinctrl@ffd13000pinctrl-single30Wf pinctrl@ffd13100pinctrl-single31 Wf rstmgr@ffd11000altr,stratix10-rst-mgr3 H iommu@fa000000arm,mmu-500arm,smmu-v23^ +eiommu disabledH spi@ffda4000snps,dw-apb-ssi 3@ cK 1Rspi^ + disabledspi@ffda5000snps,dw-apb-ssi 3P dK 2Rspi^ + disabledsysmgr@ffd12000altr,sys-mgr-s10altr,sys-mgr3  b0H timer0@ffc03000snps,dw-apb-timer q30^ -etimertimer1@ffc03100snps,dw-apb-timer r31^ -etimertimer2@ffd00000snps,dw-apb-timer s3^ -etimertimer3@ffd00100snps,dw-apb-timer t3^ -etimerserial@ffc02000snps,dw-apb-uart3  lK P^ -okayserial@ffc02100snps,dw-apb-uart3! mK Q^ -okayusb@ffb00000 snps,dwc23 ]!  &usb2-phyK # +Rdwc2dwc2-ecc^ ,eotg okayHusb@ffb40000 snps,dwc23 ^!  &usb2-phyK $ ,Rdwc2dwc2-ecc^ ,eotg okaywatchdog@ffd00200 snps,dw-wdt3 uK @^  disabledwatchdog@ffd00300 snps,dw-wdt3 vK A^  disabledwatchdog@ffd00400 snps,dw-wdt3 }K B^  disabledwatchdog@ffd00500 snps,dw-wdt3 ~K C^  disabledsdr@f8011100altr,sdr-ctlsyscon3Heccmgr:altr,socfpga-s10-ecc-manageraltr,socfpga-a10-ecc-manager   ,sdramedacaltr,sdram-edac-s100ocram-ecc@ff8cc0006altr,socfpga-s10-ocram-eccaltr,socfpga-a10-ocram-ecc3@usb0-ecc@ff8c4000.altr,socfpga-s10-usb-eccaltr,socfpga-usb-ecc3@@emac0-rx-ecc@ff8c00006altr,socfpga-s10-eth-mac-eccaltr,socfpga-eth-mac-ecc3@emac0-tx-ecc@ff8c04006altr,socfpga-s10-eth-mac-eccaltr,socfpga-eth-mac-ecc3@spi@ff8d2000!intel,socfpga-qspicdns,qspi-nor 3  P`p^ disabledusbphy0usb-nop-xceivH aliases/soc@0/serial@ffc02000/soc@0/serial@ffc02100/soc@0/timer0@ffc03000/soc@0/timer1@ffc03100/soc@0/timer2@ffd00000/soc@0/timer3@ffd00100/soc@0/ethernet@ff800000/soc@0/ethernet@ff802000/soc@0/ethernet@ff804000chosenserial1:115200n8\$memory@80000000Pmemory3 compatible#address-cells#size-cellsmodelrangesregalignmentno-mapphandledevice_typeenable-methodnext-level-cachecpu-release-addrcache-levelcache-unifiedmemory-regionfpga-mgrinterruptsinterrupt-affinityinterrupt-parent#interrupt-cellsinterrupt-controller#clock-cellsclock-frequencyinterrupt-namesmac-addressresetsreset-namesclocksclock-namestx-fifo-depthrx-fifo-depthsnps,multicast-filter-binsiommusaltr,sysmgr-sysconstatusphy-modephy-addrsnps,max-mtugpio-controller#gpio-cellsngpioscap-sd-highspeedcap-mmc-highspeedbroken-cdbus-widthreg-names#dma-cells#pinctrl-cellspinctrl-single,register-widthpinctrl-single,function-mask#reset-cellsaltr,modrst-offset#global-interrupts#iommu-cellsstream-match-maskreg-io-widthnum-cscpu1-start-addrreg-shiftphysphy-namesaltr,sdr-sysconaltr,ecc-parentcdns,fifo-depthcdns,fifo-widthcdns,trigger-address#phy-cellsserial0serial1timer0timer1timer2timer3ethernet0ethernet1ethernet2stdout-pathlinux,initrd-startlinux,initrd-end