diff -urN shoehorn-3.4/init.S shoehorn/init.S --- shoehorn-3.4/init.S Tue Aug 29 21:19:12 2000 +++ shoehorn/init.S Thu Jun 28 18:13:40 2001 @@ -19,7 +19,7 @@ */ #define SRAM_BASE 0x10000000 /* in bootstrap mode */ -#define SRAM_SIZE 0x00000800 /* CL-PS7110 has 2kB */ +#define SRAM_SIZE 0x0000c000 /* CL-PS7110 has 2kB */ .text .global _start diff -urN shoehorn-3.4/serial.c shoehorn/serial.c --- shoehorn-3.4/serial.c Wed Jan 17 02:17:01 2001 +++ shoehorn/serial.c Thu Jun 28 10:03:40 2001 @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include diff -urN shoehorn-3.4/shoehorn.c shoehorn/shoehorn.c --- shoehorn-3.4/shoehorn.c Wed Jan 17 18:22:45 2001 +++ shoehorn/shoehorn.c Fri Jun 29 15:33:49 2001 @@ -47,7 +47,7 @@ #define _POSIX_SOURCE 1 -#define MAKE_VERSION(ver) "shoehorn v"## #ver ##" built " \ +#define MAKE_VERSION(ver) "shoehorn v" #ver " built " \ __TIME__", "__DATE__ \ " (CVS: $Id: shoehorn.c,v 1.10 2001/01/17 22:50:56 miket Exp $)"; static const char version[] = MAKE_VERSION(3.4); @@ -64,7 +64,8 @@ #define RAMDISK_MAJOR 1 /* architecture numbers are defined by the ARM kernel */ -#define ARCH_NUMBER_EDB7211 50 +//#define ARCH_NUMBER_EDB7211 50 +#define ARCH_NUMBER_EDB7211 24 #define PARAM_OFFSET 0x00020000 /* immediately after video RAM */ #define PARAM_U1_OFFSET 0x00020000 @@ -76,18 +77,20 @@ #define KERNEL_OFFSET 0x00028000 /* beginning of kernel image */ #define PAGE 0x1000 -#define INITRD_START 0xc1000000 +#define INITRD_START 0xc0400000 #define ETH_STEP 1024 static int ethernet = 0; static int hardware = 0; static int terminal = 0; +static int boot = 0; struct option options[] = { { "anvil", 0, &hardware, 'a' }, { "edb7211", 0, &hardware, 'e' }, { "ethernet", 0, ðernet, 1 }, + { "boot", 0, &boot, 1 }, { "initrd", 1, 0, 'i' }, { "kernel", 1, 0, 'k' }, { "loader", 1, 0, 'l' }, @@ -479,9 +482,18 @@ target_write_word(IO(SYSCON3), (target_read_word(IO(SYSCON3)) & ~CLKCTL) | CLKCTL_73); +#if 0 printf("- 64kHz DRAM refresh\n"); /* IO_DRFPR = 0x81 */ target_write_word(IO(DRFPR), 0x81); +#else + //target_write_word(IO(SDCONF), SDR_CAS_LAT_2 | SDR_CAP_64 + //| SDR_WIDTH_16 | SDR_CLK_PERM | SDR_ENABLE); + //target_write_word(IO(SDRFPR), 0x100); + target_write_word(IO(0x2300), 0x10 | 0x20 + | 0x100 | 0x0 | 0x400); + target_write_word(IO(0x2340), 0x100); +#endif printf("- enabling UART2\n"); /* IO_PDDR = 0x10 */ @@ -517,15 +529,21 @@ serial_baud(B115200); } +#define UBRLCR2 0x14c0 /* UART Bit Rate and Line Control register --------- */ void post_edb7211(void) { + printf("Setting up UART2\n"); + target_write_word(IO(UBRLCR2), (WL_8<