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Title:          Verilog Behavioral Simulator (VBS)
Version:        1.2.0 (beta)
Entered-date:   June 20, 1995
Description:    Simulator for Verilog HDL.  Supports functions, tasks
                and module instantiation.  Still lacks a lot of features,
                but this release has enough for a VLSI student to use
                and learn Verilog.  Supports only behavioral constructs
                of Verilog and minimal simulation constructs such as
                'initial' statements.
Keywords:       Verilog, HDL, circuit, simulator
Author:         address@not.yet.available (Lay H. Tho),
                jching@aloha.com (Jimen Ching)
Maintained-by:  jching@aloha.com (Jimen Ching)
Primary-site:   sunsite.unc.edu/pub/Linux/apps/circuits
                  106k vbs-1.2.tar.gz
                  1k vbs-1.2.lsm
Alternate-site: Not Yet Available
Original-site:  None
Platform:       C, C++, flex, bison
Copying-policy: GPL
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