a8[()[,radxa,rockrockchip,rk3188 7Radxa Rockaliases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/serial@10124000h/serial@10126000p/serial@20064000x/serial@20068000/spi@20070000/spi@20074000/mmc@10214000oscillator ,fixed-clockn6xin24mgpu@10090000",rockchip,rk3188-maliarm,mali-400  buscorexokayx 5gpgpmmupp0ppmmu0pp1ppmmu1pp2ppmmu2pp3ppmmu3$video-codec@10104000(,rockchip,rk3188-vpurockchip,rk3066-vpu@   vepuvdpu (aclk_vdpuhclk_vdpuaclk_vepuhclk_vepu$cache-controller@10138000,arm,pl310-cache2@L4scu@1013c000,arm,cortex-a9-scuglobal-timer@1013c200,arm,cortex-a9-global-timer     disabledlocal-timer@1013c600,arm,cortex-a9-twd-timer    interrupt-controller@1013d000,arm,cortex-a9-gicTiLserial@10124000&,rockchip,rk3188-uartsnps,dw-apb-uart@  "zbaudclkapb_pclk@Lokaydefaultserial@10126000&,rockchip,rk3188-uartsnps,dw-apb-uart`  #zbaudclkapb_pclkAMokaydefaultqos@1012d000,rockchip,rk3066-qossyscon Lqos@1012e000,rockchip,rk3066-qossyscon Lqos@1012f000,rockchip,rk3066-qossyscon Lqos@1012f080,rockchip,rk3066-qossyscon Lqos@1012f100,rockchip,rk3066-qossyscon Lqos@1012f180,rockchip,rk3066-qossyscon Lqos@1012f200,rockchip,rk3066-qossyscon qos@1012f280,rockchip,rk3066-qossyscon Lusb@10180000,rockchip,rk3066-usbsnps,dwc2  otgotg@@  usb2-phyokayusb@101c0000 ,snps,dwc2  otghost usb2-phyokayethernet@10204000,rockchip,rk3188-emac @<  D hclkmacrefdrmiiokaydefault    ethernet-phy@0 L mmc@10214000,rockchip,rk2928-dw-mshc!@  Hbiuciu$rx-tx.Q9resetokaydefaultEQ[m~mmc@10218000,rockchip,rk2928-dw-mshc!  Ibiuciu$rx-tx.R9reset disabledmmc@1021c000,rockchip,rk2928-dw-mshc!  Jbiuciu$rx-tx.S9reset disablednand-controller@10500000,rockchip,rk2928-nfcP@  ahb disabledpmu@20004000&,rockchip,rk3066-pmusysconsimple-mfd @L<reboot-mode,syscon-reboot-mode@RBRBRB RBpower-controller!,rockchip,rk3188-power-controllerLpower-domain@7hOpower-domain@6 power-domain@8grf@20008000&,rockchip,rk3188-grfsysconsimple-mfd Lio-domains",rockchip,rk3188-io-voltage-domain disabledusbphy0,rockchip,rk3188-usb-phyrockchip,rk3288-usb-phyokayusb-phy@10c QphyclkLusb-phy@11cRphyclkLdma-controller@20018000,arm,pl330arm,primecell @  apb_pclkL:dma-controller@2001c000,arm,pl330arm,primecell @  apb_pclk disabledi2c@2002d000,rockchip,rk3188-i2c   (i2cP disableddefaulti2c@2002f000,rockchip,rk3188-i2c   )Qi2cokaydefaultrtc@51,haoyu,hym8563Q defaultxin32kact8846@5a,active-semi,act8846Zokay)default A!L!W!b!m"y!!regulatorsREG1VCC_DDROOREG2VDD_LOGB@B@REG3VDD_ARM YpL6REG4VCC_IO2Z2ZL"REG5VDD_10B@B@REG6 VDD_HDMI&%&%REG7VCC_18w@w@REG8VCCA_332Z2ZREG9 VCC_RMII2Z2ZL REG10 VCCIO_WL2Z2ZREG11 VCC18_IOw@w@REG12VCC_28**pwm@20030000,rockchip,rk2928-pwm F disableddefault#pwm@20030010,rockchip,rk2928-pwm Fokaydefault$watchdog@2004c000 ,rockchip,rk3188-wdtsnps,dw-wdt K  3okaypwm@20050020,rockchip,rk2928-pwm  Gokaydefault%pwm@20050030,rockchip,rk2928-pwm 0Gokaydefault&i2c@20056000,rockchip,rk3188-i2c `  *Ri2c disableddefault'i2c@2005a000,rockchip,rk3188-i2c   +Si2c disableddefault(i2c@2005e000,rockchip,rk3188-i2c   4Ti2c disableddefault)serial@20064000&,rockchip,rk3188-uartsnps,dw-apb-uart @  $zbaudclkapb_pclkBNokaydefault*serial@20068000&,rockchip,rk3188-uartsnps,dw-apb-uart   %zbaudclkapb_pclkCOokaydefault+saradc@2006c000,rockchip,saradc   GJsaradcapb_pclkW 9saradc-apb disabledspi@20070000(,rockchip,rk3188-spirockchip,rk3066-spiEHspiclkapb_pclk  &   $txrx disableddefault,-./spi@20074000(,rockchip,rk3188-spirockchip,rk3066-spiFIspiclkapb_pclk  ' @  $txrx disableddefault0123dma-controller@20078000,arm,pl330arm,primecell @  apb_pclkLcpusrockchip,rk3066-smpcpu@0cpu,arm,cortex-a94,@:5N6cpu@1cpu,arm,cortex-a94:5N6cpu@2cpu,arm,cortex-a94:5N6cpu@3cpu,arm,cortex-a94:5N6opp_table0,operating-points-v2YL5opp-312000000dk Yy@opp-504000000d nkHopp-600000000d#Fk~opp-816000000d0,kopp-1008000000d<kg8opp-1200000000dGk0opp-1416000000dTfrkopp-1608000000d_"kpdisplay-subsystem,rockchip,display-subsystem78sram@10080000 ,mmio-sram smp-sram@0,rockchip,rk3066-smp-sramPvop@1010c000,rockchip,rk3188-vop  aclk_vopdclk_vophclk_vop$def 9axiahbdclk disabledportL7vop@1010e000,rockchip,rk3188-vop  aclk_vopdclk_vophclk_vop$ghi 9axiahbdclk disabledportL8timer@2000e000,,rockchip,rk3188-timerrockchip,rk3288-timer   .EW pclktimertimer@200380a0,,rockchip,rk3188-timerrockchip,rk3288-timer    @BZ pclktimeri2s@1011a000(,rockchip,rk3188-i2srockchip,rk3066-i2s   default9Ki2s_clki2s_hclk::$txrx disabledsound@1011e000,,rockchip,rk3188-spdifrockchip,rk3066-spdif N mclkhclk:$tx  default;okayL@clock-controller@20000000,rockchip,rk3188-cru Lefuse@20010000,rockchip,rk3188-efuse @[ pclk_efusecpu_leakage@17pinctrl,rockchip,rk3188-pinctrl<gpio0@2000a000,rockchip,rk3188-gpio-bank0   6UTiLgpio1@2003c000,rockchip,gpio-bank   7VTigpio2@2003e000,rockchip,gpio-bank   8WTiLCgpio3@20080000,rockchip,gpio-bank   9XTiLpcfg-pull-upL>pcfg-pull-down,pcfg-pull-none;L=emmcemmc-clkH=emmc-cmdH>emmc-rstH=emacemac-xferH========L emac-mdio H==L i2c0i2c0-xfer H==Li2c1i2c1-xfer H==Li2c2i2c2-xfer H==L'i2c3i2c3-xfer H==L(i2c4i2c4-xfer H==L)lcdc1lcdc1-dclkH=lcdc1-denH=lcdc1-hsyncH=lcdc1-vsyncH=ldcd1-rgb24H========= = = = = ===========pwm0pwm0-outH=L#pwm1pwm1-outH=L$pwm2pwm2-outH=L%pwm3pwm3-outH=L&spi0spi0-clkH>L,spi0-cs0H>L/spi0-txH>L-spi0-rxH>L.spi0-cs1H>spi1spi1-clkH>L0spi1-cs0H>L3spi1-rxH>L2spi1-txH>L1spi1-cs1H>uart0uart0-xfer H>=Luart0-ctsH=uart0-rtsH=uart1uart1-xfer H>=Luart1-ctsH=uart1-rtsH=uart2uart2-xfer H> =L*uart3uart3-xfer H > =L+uart3-ctsH =uart3-rtsH =sd0sd0-clkH=Lsd0-cmdH=Lsd0-cdH=Lsd0-wpH =sd0-pwrH=sd0-bus-width1H=sd0-bus-width4@H====Lsdmmc-pwrH=LEsd1sd1-clkH=sd1-cmdH=sd1-cdH=sd1-wpH=sd1-bus-width1H=sd1-bus-width4@H====i2s0i2s0-bus`H======L9spdifspdif-txH=L;pcfg-output-lowVL?act8846act8846-dvs0-ctlH?L hym8563rtc-intH>Llan8720aphy-intH>L ir-receiverir-recv-pinH =LBusbhost-vbus-drvH=LFotg-vbus-drvH=LDmemory@60000000memory`gpio-keys ,gpio-keysapower lrt}GPIO Key Powerdgpio-leds ,gpio-ledsled-0}rock:green:user1 l offled-1}rock:blue:user2 loffled-2}rock:red:power loffsound,simple-audio-cardSPDIFsimple-audio-card,dai-link@1cpu@codecAspdif-out,linux,spdif-ditLAgpio-ir-receiver,gpio-ir-receiver l defaultBusb-otg-regulator,regulator-fixed CdefaultD otg-vbusLK@LK@sdmmc-regulator,regulator-fixed sdmmc-supply2Z2Z defaultE "Lusb-host-regulator,regulator-fixed defaultF host-pwrLK@LK@vsys-regulator,regulator-fixedvsysLK@LK@L! #address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4serial0serial1serial2serial3spi0spi1mmc0clock-frequency#clock-cellsclock-output-namesregclocksclock-namesassigned-clocksassigned-clock-ratesresetsstatusinterruptsinterrupt-namespower-domainscache-unifiedcache-levelphandleinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthpinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesrockchip,grfmax-speedphy-modephyphy-supplydmasdma-namesfifo-depthreset-namesvmmc-supplybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpoffsetmode-normalmode-recoverymode-bootloadermode-loader#power-domain-cellspm_qos#phy-cells#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstsystem-power-controllervp1-supplyvp2-supplyvp3-supplyvp4-supplyinl1-supplyinl2-supplyinl3-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-on#pwm-cells#io-channel-cellsenable-methoddevice_typenext-level-cacheclock-latencyoperating-points-v2cpu-supplyopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsrangesrockchip,playback-channelsrockchip,capture-channels#sound-dai-cells#reset-cellsrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disablerockchip,pinsoutput-lowautorepeatgpioslinux,codelabellinux,input-typewakeup-sourcedebounce-intervaldefault-statesimple-audio-card,namesound-daienable-active-highgpioregulator-boot-onstartup-delay-usvin-supply