Ð þí6Â85Ì(ö5” Hisilicon D01 Development Board!hisilicon,hip04-d01aliases,/soc/serial@4007000bootwrapper!hisilicon,hip04-bootwrapper4Ààcpuscpu-mapcluster0core0@core1@core2@core3@cluster1core0@core1@core2@core3@cluster2core0@ core1@ core2@ core3@ cluster3core0@ core1@core2@core3@cpu@0Dcpu!arm,cortex-a15PTcpu@1Dcpu!arm,cortex-a15PTcpu@2Dcpu!arm,cortex-a15PTcpu@3Dcpu!arm,cortex-a15PTcpu@100Dcpu!arm,cortex-a15PTcpu@101Dcpu!arm,cortex-a15PTcpu@102Dcpu!arm,cortex-a15PTcpu@103Dcpu!arm,cortex-a15PTcpu@200Dcpu!arm,cortex-a15PT cpu@201Dcpu!arm,cortex-a15PT cpu@202Dcpu!arm,cortex-a15PT cpu@203Dcpu!arm,cortex-a15PT cpu@300Dcpu!arm,cortex-a15PT cpu@301Dcpu!arm,cortex-a15PTcpu@302Dcpu!arm,cortex-a15PTcpu@303Dcpu!arm,cortex-a15PTtimer!arm,armv7-timer\0m   clk_50mx !fixed-clock…úð€Tclk_168mx !fixed-clock… zTclk_375mx !fixed-clock…Z ÀTsoc !simple-bus\•àinterrupt-controller@c01000!hisilicon,hip04-intcœ­ m  PÀÀ À@ À` Tsysctrl!hisilicon,sysctrlsysconPàfabric!hisilicon,hip04-fabricP dual_timer@3000000!arm,sp804arm,primecellP mà ÂÉtimer0clktimer1clkapb_pclkarm-pmu!arm,cortex-a15-pmuÀm@ABCDEFGHIJKLMNOserial@4007000!snps,dw-apb-uartPp m}ÂÉbaudclkapb_pclkÕßoksata@a000000!hisilicon,hisi-ahciP  mtetb@0,e3c42000"!arm,coresight-etb10arm,primecellPãÄ Â Éapb_pclkin-portsportendpoint@0æTetb@0,e3c82000"!arm,coresight-etb10arm,primecellPãÈ Â Éapb_pclkin-portsportendpoint@0æTetb@0,e3cc2000"!arm,coresight-etb10arm,primecellPãÌ Â Éapb_pclkin-portsportendpoint@0æT etb@0,e3d02000"!arm,coresight-etb10arm,primecellPãÐ Â Éapb_pclkin-portsportendpoint@0æT#tpiu@0,e3c05000!!arm,coresight-tpiuarm,primecellPãÀP Éapb_pclkin-portsportendpoint@0æT:replicator0 !arm,coresight-static-replicatorout-portsport@0PendpointæTport@1PendpointæT;in-portsportendpointæT&replicator1 !arm,coresight-static-replicatorout-portsport@0PendpointæTport@1PendpointæT<in-portsportendpointæT+replicator2 !arm,coresight-static-replicatorout-portsport@0Pendpointæ Tport@1Pendpointæ!T=in-portsportendpointæ"T0replicator3 !arm,coresight-static-replicatorout-portsport@0Pendpointæ#Tport@1Pendpointæ$T>in-portsportendpointæ%T5funnel@0,e3c41000+!arm,coresight-dynamic-funnelarm,primecellPãÄ Éapb_pclkout-portsportendpointæ&Tin-portsport@0Pendpointæ'T?port@1Pendpointæ(T@port@2Pendpointæ)TAport@3Pendpointæ*TBfunnel@0,e3c81000+!arm,coresight-dynamic-funnelarm,primecellPãÈ Éapb_pclkout-portsportendpointæ+Tin-portsport@0Pendpointæ,TCport@1Pendpointæ-TDport@2Pendpointæ.TEport@3Pendpointæ/TFfunnel@0,e3cc1000+!arm,coresight-dynamic-funnelarm,primecellPãÌ Éapb_pclkout-portsportendpointæ0T"in-portsport@0Pendpointæ1TGport@1Pendpointæ2THport@2Pendpointæ3TIport@3Pendpointæ4TJfunnel@0,e3d01000+!arm,coresight-dynamic-funnelarm,primecellPãРÉapb_pclkout-portsportendpointæ5T%in-portsport@0Pendpointæ6TKport@1Pendpointæ7TLport@2Pendpointæ8TMport@3Pendpointæ9TNfunnel@0,e3c04000+!arm,coresight-dynamic-funnelarm,primecellPãÀ@ Éapb_pclkout-portsportendpointæ:Tin-portsport@0Pendpointæ;Tport@1Pendpointæ<Tport@2Pendpointæ=T!port@3Pendpointæ>T$ptm@0,e3c7c000"!arm,coresight-etm3xarm,primecellPãÇÀ Éapb_pclk@out-portsportendpointæ?T'ptm@0,e3c7d000"!arm,coresight-etm3xarm,primecellPãÇРÉapb_pclk@out-portsportendpointæ@T(ptm@0,e3c7e000"!arm,coresight-etm3xarm,primecellPãÇà Éapb_pclk@out-portsportendpointæAT)ptm@0,e3c7f000"!arm,coresight-etm3xarm,primecellPãÇð Éapb_pclk@out-portsportendpointæBT*ptm@0,e3cbc000"!arm,coresight-etm3xarm,primecellPãËÀ Éapb_pclk@out-portsportendpointæCT,ptm@0,e3cbd000"!arm,coresight-etm3xarm,primecellPãËРÉapb_pclk@out-portsportendpointæDT-ptm@0,e3cbe000"!arm,coresight-etm3xarm,primecellPãËà Éapb_pclk@out-portsportendpointæET.ptm@0,e3cbf000"!arm,coresight-etm3xarm,primecellPãËð Éapb_pclk@out-portsportendpointæFT/ptm@0,e3cfc000"!arm,coresight-etm3xarm,primecellPãÏÀ Éapb_pclk@ out-portsportendpointæGT1ptm@0,e3cfd000"!arm,coresight-etm3xarm,primecellPãÏРÉapb_pclk@ out-portsportendpointæHT2ptm@0,e3cfe000"!arm,coresight-etm3xarm,primecellPãÏà Éapb_pclk@ out-portsportendpointæIT3ptm@0,e3cff000"!arm,coresight-etm3xarm,primecellPãÏð Éapb_pclk@ out-portsportendpointæJT4ptm@0,e3d3c000"!arm,coresight-etm3xarm,primecellPãÓÀ Éapb_pclk@ out-portsportendpointæKT6ptm@0,e3d3d000"!arm,coresight-etm3xarm,primecellPãÓРÉapb_pclk@out-portsportendpointæLT7ptm@0,e3d3e000"!arm,coresight-etm3xarm,primecellPãÓà Éapb_pclk@out-portsportendpointæMT8ptm@0,e3d3f000"!arm,coresight-etm3xarm,primecellPãÓð Éapb_pclk@out-portsportendpointæNT9memory@0,10000000Dmemory PÀÀ@ #address-cells#size-cellsmodelcompatibleserial0boot-methodcpudevice_typeregphandleinterrupt-parentinterrupts#clock-cellsclock-frequencyranges#interrupt-cellsinterrupt-controllerclocksclock-namesreg-shiftstatusremote-endpoint